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| CY2PD817 320-MHz 1:7 PECL to PECL/CMOS Buffer Features * * * * * * * * * * * * * DC to 320-MHz operation 50-ps output-output skew 30-ps cycle-cycle jitter 2.5V power supply LVPECL input @ 320-MHz Operation One LVPECL output @ 320-MHz Operation Four LVCMOS/LVTTL outputs @ 250 MHz/160 MHz Two LVCMOS/LVTTL outputs @ 250 MHz/80 MHz 45% to 55% output duty cycle Output divider control Output enable/disable control Operating temperature range: 0C to +85C 24-pin TSSOP Description The CY2PD817 is a low-voltage LVPECL-to-LVPECL and LVCMOS fanout buffer designed for servers, data communications, and clock management. The CY2PD817 is ideal for applications requiring mixed differential and single-ended clock distribution. This device accepts an LVPECL input reference clock and provides one LVPECL and six LVCMOS/LVTTL output clocks. The outputs are partitioned into three banks of one, two, and four outputs. The LVPECL output is a buffered copy of the input clock while the LVCMOS outputs are divided by 1, 2, and 4. When CLRDIV is set HIGH, the output dividers are set to 1. In this mode, the maximum input frequency is limited to 250 MHz. When OE is set HIGH, the outputs are disabled in a High-Z state. Block Diagram Pin Configuration VDD PCLKI PCLKI VSS VDD PCLKO PCLKO / 2, / 1 PCLKO PCLKO PCLKI PCLKI / 4, / 1 QA[0:1] QB[0:3] VSS OE CLRDIV OE VDD VSS CLRDIV 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD QA0 QA1 VSS VDD QB0 QB1 VSS VDD QB2 QB3 VSS 24 TSSOP CY2PD817 Cypress Semiconductor Corporation Document #: 38-07574 Rev. ** * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised August 28, 2003 CY2PD817 Pin Description[1] Pin 2 3 6 7 23, 22 14, 15, 18, 19 12 9 1, 5, 10, 16, 20, 24 4, 8, 11, 13, 17, 21 Table 1. Functional Table Control CLRDIV OE Name PCLKI PCLKI PCLKO PCLKO QA[1,0] QB[3:0] CLRDIV OE VDD VSS I/O I, PD I, PU/PD O O O O I, PD I, PD Supply Supply Type LVPECL LVPECL LVPECL LVPECL LVCMOS LVCMOS LVCMOS LVCMOS VDD Ground Description LVPECL reference clock input LVPECL reference clock input LVPECL clock output LVPECL clock output Bank A, LVCMOS clock outputs Bank B, LVCMOS clock outputs Clear divider input. See functional Table 1 Output enable/disable input. See functional Table 1 2.5V power supply[2] Common ground Default 0 0 0 Bank A = /4, Bank B = /2 All outputs are enabled 1 Bank A = /1, Bank B = /1 All outputs are three-stated Absolute Maximum Conditions Parameter VDD VDD VIN VOUT VTT LU RPS TS TA TJ OJC OJA ESDH FIT Description DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Latch Up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time Manufacturing test Functional Relative to VSS, with or VDD applied Relative to VSS LVCMOS outputs LVPECL output Functional Ripple Frequency < 100 kHz Non-functional Functional Functional Functional Functional 200 - -65 0 - - - 2000 10 Condition Min. -0.5 2.375 -0.5 -0.5 Max. 3.3 2.625 VDD + 0.5 VDD + 0.5 VDD / 2 VDD - 2 - 150 +150 +85 +150 42 105 - mA mVp-p C C C C/W C/W V ppm Unit V V V V V Notes: 1. PU = Internal pull up, PD = Internal pull down. 2. A 0.1-uF bypass capacitor should be placed as close as possible to each positive power pin (< 0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the trace. Document #: 38-07574 Rev. ** Page 2 of 6 CY2PD817 DC Electrical Specifications (VDD = 2.5V 5%, TA = 0C to +85C) Parameter VPP VCMR VIL VIH VOL VOH VOL VOH IIL IIH IDDQ IDD CIN COUT ZOUT Parameter fin VPP(AC) VCMR(AC) frefDC fmax Description Input Peak-Peak Voltage Input Common Mode Range Input Voltage, Low Input Voltage, High Output Voltage, Low Output Voltage, High Output Voltage, Low [3] Output Voltage, High[3] Input Current, Low[4] Input Current, High[4] Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Pin Capacitance Output Impedance Description Input Frequency Input Peak-Peak Voltage Input Common Mode Range Reference Input Duty Cycle Output Frequency PCLKO, PCLKO Bank B, CLRDIV = 0 Bank A, CLRDIV = 0 Bank A, Bank B, CLRDIV = 1 tr, tf DC Output Rise/Fall Time 20% to 80%, PCLKO, PCLKO 0.6V to 1.8V, QA, QB Output Duty Cycle, DCREF = 50% Bank A/Bank B LVPECL Output, fmax < 300 MHz LVPECL Output, fmax > 300 MHz tsk(O) Output-to-Output Skew Skew within Bank BankA to BankB Skew PECL Output to all Banks Skew TPLH TPHL tQoff tQon tJIT(CC) Propagation Delay Propagation Delay Output Disable Time Output Enable Time Cycle-to-Cycle Jitter PCLKI to PCLKO PCLKI to QA/QB PCLKI to PCLKO PCLKI to QA/QB OE to any output OE to any output LVPECL output LVTTL output Condition PCLKI, PCLKI PCLKI, PCLKI OE, CLRDIV Min. 250 1.0 -0.30 1.7 PCLKO, PCLKO, 50 to VTT 0.2 PCLKO, PCLKO, 50 to VTT VDD - 1.2 IOL = 16 mA, QA, QB -0.3 IOH = -16 mA, QA, QB 1.8 VIL = VSS - VIH = VDD - VIN = 0V, outputs disabled - Outputs loaded @ 250 MHz - - - QA, QB - Condition CLRDIV = 0 CLRDIV = 1 PCLKI, PCLKI PCLKI, PCLKI Min. 0 - 500 1.2 40 0 0 - - 200 0.1 45 45 40 - - - - - - - - - - - Typ. - - - - - - - - - - 2.5 250 4 4 25 Typ. - - - - - - - - - - - - - - 50 150 200 - - - - 3 3 |30| - Max. VDD - 1.3 VDD - 0.6 0.7 VDD + 0.3 0.8 VDD - 0.4 0.6 VDD + 0.3 -20 100 3.5 - - - - Max. 320 250 1000 VDD - 0.6 60 320 160 80 250 700 1.2 55 55 60 75 200 250 7 7 7 7 6 6 |75| |50| ns ns ps ns ns ps ps ns % mV V % MHz Unit mV V V V V V V V A A mA mA pF pF Unit MHz AC Electrical Specifications (VDD = 2.5V 5%, TA = 0C to +85C) [5, 6] Notes: 3. Driving 50 parallel terminated transmission line to a termination voltage of VTT. 4. Inputs have pull-down resistors that affect the input current. 5. AC characteristics apply for parallel output termination to VTT. Parameters are guaranteed by characterization and are not 100% tested. 6. AC test are measured with fin = 250 MHz at VDD/2 unless otherwise specified. Document #: 38-07574 Rev. ** Page 3 of 6 CY2PD817 Zo = 50 ohm Zo = 50 ohm Differential Pulse Generator Z = 50 ohm Zo = 50 ohm Differential Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm Zo = 50 ohm RT = 50 ohm Zo = 50 ohm VTT RT = 50 ohm RT = 50 ohm VTT VTT VTT VTT Differential Output Figure 1. CY2PD817 Test Reference Single-Ended Outputs PECL_CLK PECL_CLK PECL_CLK VCMR VPP VPP VCMR PECL_CLK Q tPD Differential Output Q tPD Single-Ended Outputs Figure 2. Propagation Delay (TPD) Test Reference VDD/2 VDD/2 tP tP T0 D C = tP / T 0 x 1 0 0 % T0 DC = tP / T 0 x 100% Figure 3. Output Duty Cycle V D D /2 V D D /2 tS K (0 ) Figure 4. Output-Output Skew Document #: 38-07574 Rev. ** Page 4 of 6 CY2PD817 OE Qn tQ o n tQ o ff Figure 5. Output Enable/Disable Time Ordering Information Part Number CY2PD817ZC CY2PD817ZCT Package Type 24-pin TSSOP 24-pin TSSOP - Tape and Reel Product Flow Commercial, 0C to +85C Package Drawing and Dimensions 24-lead Thin Shrunk Small Outline Package (4.40-mm Body) Z24 51-85119-** All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07574 Rev. ** Page 5 of 6 (c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2PD817 Document History Page Document Title: CY2PD817 320-MHz 1:7 PECL to PECL/CMOS Buffer Document Number: 38-07574 REV. ** ECN NO. 129024 Issue Date 08/29/03 Orig. of Change RGL New Data Sheet Description of Change Document #: 38-07574 Rev. ** Page 6 of 6 |
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